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 Home > Technology > PCB>  HDI Technology Roadmap
 
   
 
PCB
PCB HLC Technology
      Roadmap
 HDI Technology Roadmap
IC Substrate

   

    

HDI Technology Roadmap  
  Products Roadmap/ Development Schedule 
 
 
Category Item Current Capability By 2016 H2 By 2017 H1 By 2017 H2
Structure Stagger Via 5+N+5 6+N+6 6+N+6 7+N+7
Stacked Via 5+N+5 6+N+6 6+N+6 7+N+7
All Stacked Via 10 Layers 12 Layers 14 Layers 14 Layers
Max. Board
Thickness
4 Layers 250 µm 250 µm 230 µm 210 µm
6 Layers 300 µm 300 µm 280 µm 260 µm
Embedded 
(Discrete Passives)
Sample Sample Sample SVM
Routing
Density 
Line Width/Space H oz Cu 40/40 µm 40/40 µm 35/35 µm 35/35 µm
1 oz Cu 60/60 µm 55/55 µm 50/50 µm 45/45 µm
Laser Via/Pad 75/150 µm 65/115 µm 60/110 µm 60/100 µm
Router Tolerance +/-75 µm +/-50 µm +/-50 µm +/-45 µm
BGA Pitch 0.4 mm 0.35 mm 0.3 mm 0.3 mm
Material Min. Core  50 µm 50 µm 40 µm 40 µm
Min. PP  40 µm 40 µm 30 µm 30 µm
Halogen Free  NPGN150, NPGN170, NPGN150LK(HD), NPG180IN, EM355(D), S1150G
Non Halogen Free NP155F, NP175F
Surface Finish Ni/Au, Selective Ni/Au, ENEPIG, OSP, Immersion Tin, Immersion Ag

 
  Updated Date: 2016/4/1